1. Field of the Invention
The present invention relates to a TLB circuit for converting a virtual address to a physical address, particularly to a technique of judging at a high speed whether or not a virtual address which has received an access request matches a virtual address stored inside a processor.
2. Related Background Art
To eliminate a speed difference between a processor and a main memory, it is general to dispose a cache memory between them. The cache memory is incorporated in the processor in some cases, or disposed outside the processor in the other cases.
When data requested by the processor exists in the cache memory (cache hit), the data is transferred from the cache memory to the processor, and therefore, the processor does not have to access the main memory, so that the processor can perform the processing at a high speed. On the other hand, when the data requested by the processor does not exist in the cache memory, the processor has to directly access the main memory, so that it takes much time to perform the processing.
A recent processor employs a virtual address system in which a part of a virtual address space is allocated to the main memory. By employing the virtual address system, it is possible to access memory, regardless of the main memory.
The virtual address can be obtained, for example, by adding a base address and an offset address. To perform this addition, an adder is disposed in the processor. Moreover, in the processor, a TLB circuit for converting the virtual address to a physical address is disposed. The TLB circuit outputs a signal indicating whether or not the virtual address which has been received from the outside matches the virtual address stored inside.
In the recent processor, the virtual address has a large number of bits, so that it takes much time to perform the addition processing in the adder. Therefore, if the address conversion processing in the TLB circuit is started after the addition processing in the adder has been completed, much time is taken until the physical address is outputted. Therefore, when a part of the physical address is used for checking the cache hit, the process in case of the cache hit cannot be performed at a high speed.
To solve the problem, in U.S. Pat. No. 5,606,683, based on the result of addition of some bit strings of the base address and the offset address and digit overflow information, the match/mismatch of the virtual address is detected. However, also in the above-described document, the adder is used to calculate the address. Since the address conversion processing cannot be performed until the output of the adder is obtained, the cache hit check cannot be performed at a high speed.
An object of the present invention is to provide a microprocessor in which conversion from a virtual address to be accessed by the processor into a physical address can be performed at a high speed and it is possible to determine at a high speed whether or not cache hit is.
To attain the above-described object, there is provided a translation lookaside buffer (TLB) circuit for converting a virtual address to a physical address comprising:
a carry storage section for storing digit overflow information when a lower side bit string of a base address and a lower side bit string of an offset address of virtual address information as a comparison criterion are added to each other;
a upper side address storage section for storing a upper side bit string of the base address and a upper side bit string of the offset address of the virtual address information as the comparison criterion;
a carry comparator for comparing a digit overflow information when a lower side bit string of the base address and a lower side bit string of the offset address of the virtual address information which has received an access request are added to each other, with the digit overflow information stored in said carry storage section;
a upper side address comparator for detecting whether or not the upper side bit string of the base address of the virtual address information which has received the access request matches the upper side bit string of the base address stored in said upper side address storage section, and for detecting whether or not the upper side bit string of the offset address of the virtual address information which has received the access request matches the upper side bit string of the off set address stored in said upper side address storage section; and
a match detector for outputting a match signal of the virtual address only when comparison results by said carry comparator are matched and comparison results by the upper side address comparator are matched.
According to the present invention, for the lower side bit strings of the base and offset addresses, instead of comparing the addition results of both addresses, carry signals are compared, so that it can be detected at a high speed whether or not the virtual addresses are matched.
Moreover, there is provided a translation lookaside buffer (TLB) circuit for converting a virtual address to a physical address comprising:
a first storage section for storing a upper side bit string of a base address of virtual address information as a comparative criterion;
a second storage section for storing a bit string obtained by adding 1 to a upper side bit string of an offset address of the virtual address information in the case where there is a digit overflow when a lower side bit string of the base address and a lower side bit string of the offset address of the virtual address information as the comparison criterion are added to each other, and for storing the upper side bit string of the offset address of the virtual address information in the case where there is no digit overflow;
a third storage section for storing the upper side bit string of the offset address of the virtual address information in the case where there is the digit overflow when the lower side bit string of the base address and the lower side bit string of the offset address of the virtual address information as the comparison criterion are added to each other, and for storing the bit string obtained by subtracting 1 from the upper side bit string of the offset address of the virtual address information in the case where there is no digit overflow;
a first comparator for comparing the upper side bit string of the base address of the virtual address information which has received the access request, with the bit string stored in said first storage section;
a second comparator for comparing the lower side bit string of the base address of the virtual address information which has received the access request, with the bit string stored in said second storage section;
a third comparator for comparing whether or not the lower side bit string of the base address of the virtual address information which has received the access request matches the bit string stored in said third storage section; and
a match detector for outputting a signal indicating whether or not the virtual address which has received the access request matches the virtual address as the comparison criterion on the basis of comparison results of said first to third comparators.
Moreover, according to the present invention, after the offset address is regulated in accordance with a value of carry signal, the addresses are compared. Therefore, regardless of the presence/absence of a carry, it is possible to accurately compare the virtual addresses.